1. Field of the Invention
The present invention relates to a semiconductor device and a method for manufacturing the same. More specifically, the present invention relates to semiconductor devices in an integrated circuit (IC) comprising high- and low-voltage transistors and a method for manufacturing such semiconductor devices.
2. Discussion of the Related Art
Source driver integrated circuits (ICs) are useful as display driver integrated circuits. Such source driver ICs vary slightly in power supply voltage regions, depending on the application(s) of the IC. Notebook computers have a low-voltage operational region of about 3.3V and a high-voltage operational region of about 13.5V. LCD TVs have a low-voltage operational region of about 3.3V and a high-voltage operational region of about 20V. For the purpose of meeting such operational requirements, display driver integrated circuits generally comprise at least two of p- and n-type high-voltage transistors and p-type and n-type low-voltage transistors (e.g., one p-type or n-type high-voltage transistor and one p-type or n-type low-voltage transistor).
Hereinafter, related semiconductor devices to prevent and reduce latchup in such integrated circuits will be described with reference to the annexed drawings.
FIG. 1 is a schematic view of a general integrated circuit to illustrate latchup, wherein the integrated circuit comprises a P-well 10, an N-well 20, high-concentration n-doped regions (N+) 30 and 40, and high-concentration p-doped regions (P+) 32 and 42.
Referring to FIG. 1, in complementary metal oxide semiconductor (CMOS) transistors utilizing dual P and N wells 10 and 20, a parasitic PNPN-type silicon controlled rectifier (SCR) is formed between power supplies (VDD and VSS). Such a parasitic SCR element may turn on, when semiconductor integrated circuits operate. In addition, once the parasitic SCR turns on, it turns off only if the power supply ceases. For this reason, important reliability problems may occur.
In FIG. 1, the value obtained by multiplying a gain of a parasitic NPN transistor (Qnpn) by a gain of a parasitic PNP transistor (Qpnp) should be at least 1 in order to result in a latchup condition. The PNPN SCR may readily latch up when the p-type well resistance (Rpsub) and the n-type well resistance (Rnwell) increases.
FIG. 2 is a cross-sectional view illustrating a related integrated circuit to prevent latchup, wherein the integrated circuit comprises a substrate 50, n-type wells 60 and 64, p-type wells 62 and 66, device isolation films 70 to 78, high-concentration impurity-doped regions 90 to 98 and gate patterns 80 and 82.
The related integrated circuit shown in FIG. 2 comprises additional guard rings comprising high-concentration impurity-doped regions 93 and 94 to reduce gain elements of parasitic NPN transistor (Qnpn) and parasitic PNP transistor Qpnp. That is, an increase in the distance x shown in FIG. 2 prevents two parasitic transistors (i.e., parasitic NPN and PNP transistors Qnpn and Qpnp) from simultaneously operating. The double guard rings 93 and 94 shown in FIG. 2 are commonly adopted to prevent occurrence of latchup on input/output (I/O) terminals where electrostatic discharge (ESD) protection circuits are present. However, when an inner driver stage or core stage also adopts double guard rings, the chip size of integrated circuits increases. For this reason, it is disadvantageous to apply the guard ring structure to the core stage.